Memory Giants Split Over 4F² DRAM Strategy

U.S. chipmaker Micron abandons commercialization of the ‘4F² (4F square)’ cell structure. As United States-based Micron abandons the commercialization of the ‘4F² (4F Square)’ cell structure, which has been considered a core technology for next-generation DRAM, the technological development strategies of the top three global memory semiconductor companies are diverging. Unlike Samsung Electronics and SK hynix, which are continuing the development of 4F², Micron has decided to focus on the advancement of existing processes and three-dimensional (3D) DRAM. With DRAM miniaturization approaching its physical limits, the future competitive landscape is expected to shift depending on these technological choices. According to the semiconductor industry and foreign media on Oct. 26, Micron revealed its memory technology roadmap for the next 10 years during a technology webinar on Oct. 21 (local time) and announced its policy not to adopt 4F². Scott DeBoer, Executive Vice President and Chief Technology and Product Officer (CTPO) of Micron, explained that while the company has researched the technology for more than 20 years, it has decided not to pursue commercialization due to process complexity, increased costs, and the fundamental limits of miniaturization. 4F² is a technology that theoretically reduces the area occupied by a single DRAM cell by about 33% compared to the existing 6F² structure. It has been cited as a key technology for next-generation DRAM miniaturization because it can increase integration density by reducing the cell area. However, Micron determined that reducing the cell area does not directly translate to an actual improvement in integration density. The company noted that DRAM integration density is determined not only by the transistor structure but also by the spacing of the capacitors that store electrical charges, and that applying 4F² could increase manufacturing costs and process complexity. During the webinar’s question-and-answer session, CTPO DeBoer evaluated the claim that 4F² provides practical advantages over 6F² as being “somewhat close to a myth.” He explained that while the implementation of 4F² is possible in past processes, it leads to increased costs and complexity, adding that the industry faces physical miniaturization limits as it moves toward advanced processes. Instead, Micron plans to focus on developing wafer bonding and 3D DRAM while improving the existing 6F² structure. Following the 1-gamma (1γ) process currently in mass production, the company is scheduled to begin mass production of next-generation 1-delta (1δ) DRAM in the second half of 2027. For the subsequent 1-epsilon (1ε) process, Micron plans to increase integration density by introducing bonding technology that combines different wafers. In the long term, the company intends to transition to 3D DRAM, which stacks memory cells vertically, while determining the commercialization timing based on considerations of manufacturing costs and performance. On the other hand, Samsung Electronics and SK hynix are sustaining their development of 4F² technology. Samsung Electronics is researching technology to reduce cell area by utilizing Vertical Channel Transistors (VCT), and SK hynix is also promoting the development of a next-generation cell structure based on Vertical Gates (VG). While both companies are also researching 3D DRAM in the long term, they differ from Micron in that they are maintaining 4F² as a candidate for next-generation technology. The pursuit by Chinese companies is also a variable. China’s ChangXin Memory Technologies (CXMT) previously announced plans to introduce 4F²-based server DDR5 memory modules at the end of this year. However, specific product performance, mass production yields, and manufacturing cost competitiveness remain unconfirmed at this stage. Accordingly, the competition for next-generation DRAM is expected to evolve beyond simple circuit miniaturization into a contest of integration density improvement effects and mass production economics by technology. In particular, the key issue will be which method among cell area reduction through 4F², existing process improvement, and 3D stacking will secure higher integration density and lower production costs. Samsung Electronics recently publicly confirmed its position to continue the development of 4F² technology. Song Jae-hyuk, President and Chief Technology Officer (CTO) of Samsung Electronics’ Device Solutions (DS) Division, answered “Yes” when asked about the continuation of 4F² technology development at the Semiconductor Exhibition (SEDEX 2026) on Oct. 14. Regarding the specific progress of the development, he spared his words, stating, “We are working hard.”