Merged for Linux 7.4 Git and marked for back-porting to Linux 7.2/7.3 stable is a regression fix affecting at least the AMD Ryzen AI 9 HX 370 "Strix Point" laptop SoC when making use of Cache Aware Scheduling.
With a bug report going back to August, Cache Aware Scheduling was found to have caused problems on an AMD Ryzen AI 9 HX 370. The user reporting the problem was running Gentoo and found that during code compilation workloads of using LLVM Clang with full link-time optimizations (LTO), processes started on the efficiency "little" cores would not be moved to the larger performance cores. For the Clang LTO tasks in particular, they were frequently bound to the smaller cores. The Ryzen AI 9 HX 370 is 12 cores made up of four Zen 5 cores and eight Zen 5C cores.
The bug report successfully demonstrated the Clang LTO performance regressing on newer Linux kernels with Cache Aware Scheduling than without. Besides the denser Zen 5C cores only clocking up to 3.3GHz rather than ~5.1GHz, the Zen 5C cores share a cache half the size of the larger cores.
With a patch merged to the Linux kernel yesterday, the problem should be resolved. Cache Aware Scheduling will now honor asymmetric packing on hybrid systems, The patch explains the change:
"A regression was reported on an AMD Ryzen AI HX 370 running a cache intensive Clang full-LTO link. The little cores run at a much lower frequency (3.3 GHz vs 5.1 GHz) and have only half of the L3 cache (8 MB vs 16 MB), so pinning such a task to the little-core LLC hurts twice, and full-LTO builds slow down dramatically compared to pre-cache-aware-scheduling kernels.Asym packing and cache aware scheduling express conflicting placement strategies. Asym packing wants a task to run on the highest priority CPU, whereas cache aware scheduling wants to co-locate the tasks of a process on one LLC regardless of the priority of CPUs in that LLC.
When asym packing tries to migrate task to an idle core that has higher priority than source cpu, let asym packing win. Moving tasks to a higher performing idle core will buy more performance than cache co-location.
Prioritize asym packing over LLC balancing for regular and active load balancing."
The fix was merged via the scheduler fixes pull request on Sunday. While the Ryzen AI 9 HX 370 is under focus given the subject of the bug report, this Cache Aware Scheduling fix may also end up helping other Ryzen SoCs too with a mix of Zen 5/5C cores.